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march 2008 rev 1 1/42 AN2708 application note 2x36 w digital dimmable ball ast with l6574 and st7fdali introduction this document describes a high-efficiency, high power factor, low thd and digital dimming electronic ballast designed to drive 2x36 w t8 tube lamps. the system consists of three main blocks: the high-frequency ballast includes an active power factor correction circuit based on the l6562 for universal input voltage as well as a ballast control circuit based on the l6574. the digital dimming is performed by interfacing the st7fdali microcontroller with the analog half-bridge driver. the dali control unit is dedicated to address the slaves, to display the lamp status and to send the dimming commands. this unit is provided with a keyboard which allows setting different dimming scenes over a wide range (5-100%) as well as putting in standby and restarting the ballast. the dali communication protocol includes single and group mode, as well as broadcast mode to address the slaves. the ac-dc adapter is based on the viper12a-e. this is an offline double-output isolated power supply in dcm flyback configuration. the outputs are set for 20 v to supply the communication bus and for 5 v to supply the master microcontroller. the three blocks are described in detail and their performances are shown. in addition some of dali basics are explained. www.st.com
contents AN2708 2/42 contents 1 block diagram and system op erating conditions . . . . . . . . . . . . . . . . . 5 2 high-frequency ballast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 pfc converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 half-bridge inverter and ballast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.1 lamp dimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2.2 supply section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.3 lamp turn-on and lamp turn-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.4 verification of lamp status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.5 ballast performances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3 dali master unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.1 master unit schematic and bill of material . . . . . . . . . . . . . . . . . . . . . . . . 26 4 basics of dali . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5 dali master ac-dc adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.1 adapter description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2 adapter bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.3 adapter performances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.3.1 steady state tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.3.2 startup behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.3.3 dynamic load tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.3.4 line regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.3.5 load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.3.6 efficiency variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.3.7 conducted emissions test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
AN2708 list of tables 3/42 list of tables table 1. system operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. ballast-slave communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3. ballast bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 4. pfc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 5. power stage design equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 6. l6562 biasing circuitry design equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 7. lamp parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 8. l6574 biasing circuitry design equations for operating conditions . . . . . . . . . . . . . . . . . . . 16 table 9. ballast performances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 10. master unit bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 11. smps operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 12. adapter bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 13. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
list of figures AN2708 4/42 list of figures figure 1. system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. 2x36 w digital dimmable ballast with l6574 and st7fdali . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. ballast schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4. pfc performances at 230 v ac -50 hz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 5. lamp ballast model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 6. ballast transfer functions (magnitude) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 7. dali protocol brightness values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 8. ballast controls timing chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 9. idle state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 10. turn-on procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 11. turn-off procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 12. forward frame timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 13. backward frame timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 14. ballast startup at 230 v ac -full power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 15. lamps turn-on at 230 v ac -full power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 16. lamps running at 230 v ac - full power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 17. polling keyboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 18. pressed button event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 19. master unit schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 20. cable wiring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 21. master flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 22. slave flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 23. adapter schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 24. adapter pcb layout - top side -silkscreen (to scale). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 25. adapter pcb layout - bottom side - copper tracks (to scale) . . . . . . . . . . . . . . . . . . . . . . . 34 figure 26. flyback transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 27. viper12a-e steady state behavior at full load at 110 v ac - 60 hz . . . . . . . . . . . . . . . . . . 36 figure 28. viper12a-e steady state behavior at full load at 230 v ac - 50 hz . . . . . . . . . . . . . . . . . . . 36 figure 29. viper12a-e steady state behavior at minimum load at 110 v ac - 60 hz . . . . . . . . . . . . . . 36 figure 30. viper12a-e steady state behavior at minimum load at 230 v ac - 50 hz . . . . . . . . . . . . . . 36 figure 31. startup waveforms at full load at 110 v ac - 60 hz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 32. startup waveforms at full load at 230 v ac - 50 hz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 33. startup waveforms at minimum load at 110 v ac - 60 hz . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 34. startup waveforms at minimum load at 230 v ac - 50 hz . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 35. dynamic load waveforms at 110 v ac - 60 hz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 36. dynamic load waveforms at 230 v ac - 50 hz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 37. line regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 38. load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 39. efficiency variations vs. input voltage at full load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 40. conducted emissions at 110 v ac 60 hz - full load - line 1 peak detector . . . . . . . . . . . . . . 40 figure 41. conducted emissions at 110 v ac 60 hz - full load - line 2 peak detector . . . . . . . . . . . . . 40 figure 42. conducted emissions at 230 v ac 50 hz - full load - line 1 peak detector . . . . . . . . . . . . . . 41 figure 43. conducted emissions at 230 v ac 50 hz - full load - line 2 peak detector . . . . . . . . . . . . . 41
AN2708 block diagram and system operating conditions 5/42 1 block diagram and system operating conditions figure 1 shows the block diagram of the system. sci communication is considered as an option. figure 1. system block diagram sci communication option high frequency ballast ac dc adapter master unit
block diagram and system operating conditions AN2708 6/42 the present system has been designed acco rding to the following specifications: in addition to the previous specs, the dali communications are optically isolated, the digital dimming is performed with high precision, and the lamp filament preheating time is programmable as well as the ignition time. figure 2. 2x36 w digital dimmable ballast with l6574 and st7fdali table 1. system operating conditions parameter value input voltage range 176-265 vac/50 hz; 90-140 vac/60 hz lamp type 2x36 w t8 tube lamps circuit power (max) 80 w lamp power (max) 72 w dimming range 5% to 100% power factor > 0.99 current thd < 10% warm start < 1.5 sec standby mode power < 0. 6 w high frequency ballast ac dc adapter master unit ac dc adapter master unit
AN2708 high-frequency ballast 7/42 2 high-frequency ballast this section describes the high-frequency ballast board which includes the power factor correction stage, the half-bridge inverter driving circuitry, the output stage and the dali slave unit. the schematic of the board is shown in figure 3 . figure 3. ballast schematic c45 100nf 5vdd r26_2a 180k 5vdd 5vdd 1% r69 1k 1% r70 1k 1% + 1 + 3 + 5 + 7 + 9 + 2 + 4 + 6 + 8 + 10 j5 icp connector d17 bas16 d11 1n4148 + c46 22uf 20v r67 10k 1% 5vdd 1 8 l1 1.8mh ic_gnd sign sign r14 10e d15 1n4007 1a 1000v + cin1 3.3uf 450v ic_gnd d13 stth 1l06 rf 15k en1 rlow 4.7k en2 1 2 3 j1 con3 250v r23 330e c1 100nf r29_1 15k c9 100nf on air on air 5vdd + c42 2.2uf16v + cf 4.7uf 2 1 3 q2 stp8nm50 + cin2 3.3uf 450v 630v r30_1 100k ic_gnd r12 120k pb2 2 1 3 q3 stp8nm50 s 1 s 2 fb 3 vdd 4 d 5 d 6 d 7 d 8 u8 viper12a r30_2 100k l3 1.8mh 1 8 l2 1.8mh d3 1n4148 dz1 15v en1 out 14 rpre 2 opin+ 7 gnd 10 cpre 1 hvg 15 vboot 16 vs 12 opin- 6 opout 5 ring 4 lvg 11 en1 8 en2 9 cf 3 u2 l6574 ic_gnd ic_gnd pb1 0.5w 240ma ic_gnd 1% ic_gnd d61 bat46 rs= max 5 ohm @100khz sign 0.6w 0.6w sign c72 33nf pb1 c73 68pf red r100 68k ntc 15e@25 3a 50v green 1 2 3 4 5 6 7 j2 con7 50v vin 3 vout 1 gnd 2 u7 le50cz 1% r22 10e r19 10k ic_gnd c13 1000nf 25v c12 470pf 50v ic_gnd r18 68k neutral rs1 0.82e 5vdd cf b 22nf 25v c16 10nf 25v 1 4 3 2 -+ bridge w08g ic_gnd t1: boost inductor spec (itacoil e2543/e) - e25x13x7 core, 3c85 f errite - 1.5mm gap f or 0.7mh primary inductance - primary : 105 turns (20 x 0.1mm) - secondary : 11 turns (0.1mm) r1 750k r2 750k 50v r3 10k c20 8.2nf c2 10nf 4 cs gnd 6 3 mu lt inv 1 comp 2 7 gd 8 vcc zcd 5 u1 l6562 u1 r16 68k c3 330n c4 1000n c14 100nf c11 1nf r5 180k r6 68k r4 180k d6 bat46 + c7 4.7uf d9 bat46 + c6 47uf pwm0 r7 33e r9 750k r25 470e r10 750k d2 stth 1l06 r13 47k r8 12k 1 2 3 q1 stp8nm50 r11 9.53k r17 22e 1w r21 10e ic_gnd 1 2 3 4 lamp2 t8 36w line 1w vss_stdali ic_gnd ic_gnd c10 4.7nf 1 2 3 4 lamp1 t8 36w rs2 0.82e r24_1 680k rs_1 1e r24_2 680k fuse 4a/250v 600v 1a ic_gnd r26_2 750k ic_gnd 1w pb2 1w d5 bat46 d14 stth1l06 + c15 330uf 25v d7 bat46 r27_2 750k c19 100nf 1% 1% 1600v 50v 1% r26_1 750k + cout 10uf 25v 1% c5 100n r27_1 750k 1% 1w rup 120k 1% r28_2 4.7k r15 10k 600v 1a dz2 15v 0.5w ic_gnd 1% + cvdd 10uf 25v ic_gnd en2 c8 100nf ic_gnd r28_1 4.7k 5 4 8 1 t1 transformer l1&l2: choke inductor - e25x13x7 core - 2.62mm gap f or 1.8mh inductance - 267 turns (awg 40) 400v r29_2 15k r20 1k d8 1n4148 c17 100nf rs_2 1e d12 18v 0.5w c21 100nf c18 8.2nf ic_gnd l4 680uh 250v vss_st7dali d18 bzx284c 2v7 ic_gnd 5vdd 1 2 3 4 5 6 7 j4 con7 pb2 c44 100nf 50v en1 r60 0 r68 0 1600v r71 1k21 1% en2 ic_gnd 5vdd 1 1 2 2 3 3 4 4 u9 sfh6156-2 5vdd 1 4 2 3 - + d16 mb2s pin3 sfh6156-2 pwm0 pb2 dali bus r64 2k49 r63 2k49 pin3 sfh6156-2 5vdd en2 en1 pwm0 3 1 2 q4 bc817-25 ic_gnd ic_gnd + c43 1uf 16v 1 2 j3 con2 ic_gnd r66 4r7 1% d10 bat46 d4 1n4148 95ma r65 332r 1% r72 3k16 1% ic_gnd 1 1 2 2 3 3 4 4 u10 sfh6156-2 ic_gnd r61 11k 1% ld2 hsmg-c670 ld1 hsms-c670he ic_gnd ic_gnd reset reset 0.5w vss 1 vdd 2 reset 3 ss/ain0/pb0 4 sck/ain1/pb1 5 miso/ain2/pb2 6 mosi/ain3/pb3 7 clkin/ain4/pb4 8 ain5/pb5 9 daliin/ain6/pb6 10 pa7/daliout 11 pa6/mc0/iccclk/break 12 pa4(hs)/atpwm2 14 pa5(hs)/atpwm3/iccdata 13 pa3(hs)/atpwm1 15 pa2(hs)/atpwm0 16 pa1(hs)/atic 17 pa0(hs)/ltic 18 osc2 19 osc1/clkin 20 u11 st7fdalif2m6 r62 4k7
high-frequency ballast AN2708 8/42 this block is essentially a "double board" as the dali slave board and its external circuitry are mounted on a small separated board which is connected to the bottom side by means of a 7-pin connector. ta b l e 2 shows the ballast-sla ve communication. table 2. ballast-slave communication pin ref. description analog stage microcontroller 1 pwm0 (ref op-amp) 2 disable l6574 en1 & disconnected lamp 3 enable l6574 en2 & not ignited lamp 4gnd 55 vdd 6 pb2 disable pfc 7 sign (lamp failure) table 3. ballast bill of material reference value description bridge w08g 1.5 a 800 v bridge rectifier cout, cvdd 10 f 25 v electrolytic cap c7,cf 4.7 f 50 v electrolytic cap cfb 22 nf 25 v ceramic cap cin1,cin2 3.3 f 450 v electrolytic cap c1 100 nf 400 v polyester cap c2 10 nf 50 v ceramic cap c3 330 nf 50 v ceramic cap c4 1000 nf 50 v ceramic cap c5,c8,c9,c1 9 100 nf 50 v ceramic cap c6 47 f 450 v electrolytic cap c14 100 nf 100 v ceramic cap c10 4.7 nf 100 v ceramic cap c11 1 nf 630 v evox rifa polypropylene cap rs max = 5 ? at 100 khz c12 470 pf 50 v ceramic cap c13 1 f 50 v ceramic cap c15 330 f 25 v electrolytic cap c16 10 nf 25 v ceramic cap c17, c21 100 nf 250 v polyester cap c18,c20 8.2 nf 1600 v polyester cap c42 2.2 f16 v electrolytic cap
AN2708 high-frequency ballast 9/42 c43 1 f 20 v smd tantalum cap c44,c45 100 nf 50 v 0805 smd cap c46 22 f 20 v smd tantalum cap c72 33 nf 50 v 0805 smd cap c73 68 pf 50 v 0805 smd cap dz1,dz2 15 v 0.5 w zener diode d2,d13,d14 stth1l06 stmicroelectronics ultrafast high voltage rectifier 1 a 600 v d3,d4,d8,d1 1 1n4148 small signal rectifier 200 ma 100 v d5,d6,d7,d9 , d10,d61 bat46 do 35 stmicroelectronics small signal schottky diode d12 18 v 0.5 w zener diode d15 1n4007 1 a 1000 v general purpose rectifier d16 mb2s 0.5 a 200 v smd bridge rectifier d17 bas16 small signal diode d18 bzx284c 2v7 0.5 w zener diode fuse 4 a 250 v radial fuse j1 input 250 v connector 3-way pcb screw terminal, 5.08 mm j2 ballast-slave connector 7-way strip line socket j3 dali bus 2-way vertical pcb header, 3.81 mm pitch j4 ballast-slave connector 7-way strip line connector j5 icp connector 10-way 2-row vertical through-hole boxed header j13 4-way strip line socket j14 4-way strip line connector lamp 1 lamp connector 4-way pcb screw terminal, 5.08 mm lamp 2 lamp connector 4-way pcb screw terminal, 5.08 mm ld1 ls m67k-h2l1-1 2 ma red led smd 0805 ld2 lg m67k-g1j2-24 2 ma green led smd 0805 l1,l2 1.8 mh choke inductor 2.62 mm gap, 267 turns (awg40); e25x13x7 l3 1.8 mh 95 ma epcos bc series axial inductor l4 680 h 240 ma epcos lbc series axial inductor ntc 15 ? at 25 c 3 a inrush current suppressor q1,q2,q3 stp8nm50 to220 stmicroelectronics n-channel 550 v 0.7 ? - 8 a mdmesh mosfet table 3. ballast bill of material (continued) reference value description
high-frequency ballast AN2708 10/42 q4 bc817-25 npn small signal bipolar rs_1,rs_2 1 ? 0.6 w 1% metal film resistor rs1,rs2 0.82 ? 1 w resistor r29_1, r29_2,rf 15 k ? resistor r28_1, r28_2,rlow 4.7 k ? resistor r12,rup 120 k ? resistor r1,r2,r9, r10, r26_1, r26_2, r27_1, r27_2 750 k ? 0.6 w 1% resistor r15,r19 10 k ? resistor r3 10 k ? 0.6 w 1% resistor r4,r5, r26_2a 180 k ? resistor r6,r16,r18 68 k ? resistor r7 33 ? resistor r8 12 k ? resistor r11 9.53 k ? 1% resistor r13 47 k ? resistor r14,r21,r22 10 ? resistor r17 22 ? 1 w resistor r20 1 k ? resistor r23 330 ? resistor r25 470 ? resistor r60,r68 0 ? smd resistor 0805 r61 11 k ? 1% smd resistor 0805 r62 4.7 k ? 1% smd resistor 0805 r63,r64 1 k ? 1% smd resistor 0805 r65 330 ? 1% smd resistor 0805 r66 4.7 ? 1% smd resistor 0805 r67 10 k ? 1% smd resistor 0805 r69,r70 1 k ? 1% smd resistor 0805 r71 1.2 k ? 1% smd resistor 0805 r72 3 k ? 1% smd resistor 0805 table 3. ballast bill of material (continued) reference value description
AN2708 high-frequency ballast 11/42 note: resistors are 0.25 w unless specified. q1 , q2 &q3 are mounted with 8 c/w heatsink. 2.1 pfc converter this block allows drawing a quasi-sinusoidal current from the mains, in phase with the line voltage in order to get a pf very close to 1 (more than 0.99). to achieve such high pf the boost topology is implemented because of the advantages it offers: minimum number of external components, thus making it a low-cost solution low input di/dt thus minimizing the noise generated at the input and, therefore, the requirements on the input emi filter the switch is source-grounded, therefore is easy to drive however, boost topology requires the dc output voltage (400 vdc) to be higher than the maximum expected line peak voltage. st's l6562 has been used as the driver. it implements a transition mode control (fixed on time, variable frequency), that, for such output power, is preferred to the fixed frequency average current mode being simpler and cheaper. the circuit operates on the boundary between continuous and discontinuous current mode. besides providing good results in terms of power factor, this ic considerably reduces the total harmonic distortion (thd) as it reduces the conduction dead-angle that occurs to the ac input current near the zero-crossings of the line voltage. r100 68 k ? 1% smd resistor 0805 r24_1,r24_ 2 680 k ? resistor r30_1,r30_ 2 100 k ? 2 w resistor t1 transformer choke boost inductor (itacoil e2543/e) u1 l6562n stmicroelectronics transition-mode pfc controller u2 l6574 stmicroelectronics ballast driver u7 le50cz to-92 stmicroelectronics very low drop voltage regulators u8 viper12a-e dip8 stmicroelectronics offline smps primary ic 730 v 0.4 a 27r u9,u10 sfh6156-2 optocoupler u11 st7fdalif2m6 so20 stmicroelectronics 8-bit mcu with single voltage flash memory, data eeprom, adc, timers, spi, dali table 3. ballast bill of material (continued) reference value description
high-frequency ballast AN2708 12/42 the basic design specifications are listed in ta bl e 4 . for reference, it is useful to define also the following quantities: input power: pi (= po / ) 80 w maximum mains rms current: iirms (= pi/virms(min)) 1 a rated output current: io (= po/vo) 0.2 a the design guidelines are deeply explained in an966 ("l6561, enhanced transition mode power factor corrector"), an1757 ("switching from the l6561 to the l6562) and an1089 ("control loop model of l6561-based tm pfc"). the main design formulas are summarized as follows in ta bl e 5 . table 4. pfc operating conditions parameter value mains voltage range: virms(min) - virms(max) 90 ? 265 vac regulated dc output voltage: vo 400 vdc rated output power: po 75 w minimum switching frequency: f sw 35 khz maximum outpu t voltage ripple: ? vo < 10 v maximum overvoltage admitted: ? v ovp 60 v expected efficiency: pfc > 90 v table 5. power stage design equations input capacitor (c1) boos t inductor power mosfet (q1) boost diode (d1) where where where output capacitor (c6) c1 irms 2 fsw r vinrmsmin ??? ------------------------------------------------------------------------ = r 0.01 0.1 = l v 2 irms vo 2 virms ? ? () ? 2f sw pi vo ??? ------------------------------------------------------------------------------ = volume 4k l i 2 irms ?? k1410 3 ? ie igap ------------ - ?? ? pcu 4 3 -- - i 2 irms rcu ? ? = b v dss vo ? v ovp vm in arg ++ = pon i 2 qrms r ds on () ? = i qrms 2 2 iirms 1 6 -- - 42 9 ---------- - virms vo ---------------- - ? ? ? ? = pcross vo iirms t fall f sw ??? = pcap 3.3coss v 1.5 drain 1 2 -- - cd v 2 drain ? + ? ?? ?? f sw ? = v rrm 1.2 vo ? = i f 3io ? = p losses v t i dc rd i 2 rms ? + ? = c6 po 4 fvo ? vo ?? ? ------------------------------------------------- -
AN2708 high-frequency ballast 13/42 the pfc preregulator performances are shown in the following graphs: figure 4. pfc performances at 230 vac-50 hz table 6. l6562 biasing circuitry design equations pin 1 (inv) pin 2 (comp) pin 3 mult pin 4 (cs) a rc-c network is placed between this pin and pin 1, leading to a low crossover frequency (some tens of hertz) as well as to an adequate phase margin. a small capacitor of 10 nf filters the signal on mult pin. pin 5 (zcd) pin 6 (gnd) pin 7 (gd) pin 8 vcc ic ground. as a layout hint, this pin has to be kept separated from power ground. all the ic signals have to be referred to this pin. gate driver. a "bleeder" resistor between the gate and the source is used to avoid undesired switch-on, without affecting the power consumption. the supply voltage is provided by a capacitive power supply connected to the half-bridge inverter. ? ovp r high 40 10 6 ? ?? = v out 2.5 r high r low + () r low ------------------------------------------ - ? = rlow v multpkx 250 10 6 ? ? -------------------------------- 2.5 250 10 6 ? ? ------------------------------ = = r low r low r high + ------------------------------------- - 2.5 2v inrmsmax ? ----------------------------------------------- - = r sense 1.65 2.5 v inrmsmin v inrmsmax --------------------------------- ? ?? ?? ?? ? 22i inrms ?? ------------------------------------------------------------------------- pd rs i 2 qrms ? = m vout 2 v inrmsmax ? ? () 2.1 1.15 ? ------------------------------------------------------------------------ = r6 vout 2 v inrmsmin ? ? () m310 3 ? ?? ---------------------------------------------------------------------- - r start v inrmsmin 2 ? i startup ---------------------------------------------- = ch1 (yellow): rectified input voltage ch2 (blue): input current
high-frequency ballast AN2708 14/42 2.2 half-bridge inverter and ballast a voltage fed series resonant half-bridge inverter has been implemented to drive the tubes. this topology allows to eas ily operates in zero-voltage switching (zvs) resonant mode, heavily reducing the transistor switching losses and the electromagnetic interference. in addition it guarantees design simplicity and low cost. a parallel configuration has been chosen for the output stage. the half-bridge inverter operating conditions and the ballast design have been obtained by assuming, for each lamp, the following basic model: figure 5. lamp ballast model to increase the life time of the lamps a current mode preheat was preferred. the preheating current brings the cathodes to the correct temperature, then a high voltage ignites the lamp and finally the correct current guarantees the running power. these phases are ensured by changing the frequency of the input voltage and properly selecting v in , l and c. during preheating and ignition, the lamp is not conducti ng and the circuit is reduced to a series l-c. during running, the lamp is conducting and the circuit is an l in series with a parallel r-c. to determine the optimum values for l and c and to calculate the ballast operating frequencies the transfer functions for each mode of operation have to be inspected. the table below shows the parameters and the values for a t8 36 w tube lamp which need to be known in order to calculate the ballast operating conditions. table 7. lamp parameters parameter value input dc bus voltage: vdc 400 v preheat current: iph 0.6 a preheat time: tph 1 sec max preheat voltage: vphmax 300 vpk ignition voltage: vign 800 vpk running lamp power: prun 34 w running lamp voltage: vrun 144 vpk expected efficiency: 95%
AN2708 high-frequency ballast 15/42 once the lamp and its parameters have been chosen, the ballast design will be optimized by selecting the resonant components l and c as follows: set tpre select frunmin (> 20 khz) choose ? f = fmax-frunmin select l & c such that fph > frun select half-bridge switches select l6574 biasing circuitry the magnitude of the transfer function (lamp voltage divided by input voltage) for the two circuit configurations (preheating-ignition and running) illu strates the operating frequencies and where they lie with respect to one another. figure 6. ballast transfer functions (magnitude) the currents and voltages corresponding to the resulting operating frequencies determine the maximum current and voltage ratings for the inductor, capacitor, and the switches, which, in turn, directly determine the size and cost of the ballast. moreover the zero-voltage switching is ensured as shown by the curves above in figure 6 . stp8nm50 (8 a, 550 v) has been selected as power switch according to the current stress and the input dc voltage. the half-bridge inverter driving circuitry is based on the high performance l6574 which is an off-line half-bridge driver designed in 600 v bcd technology, including all the features needed to drive and properly control the tubes. a dedicated timing section in the l6574 allows setting the necessary parameters for proper preheat and ignition of the lamps. also, an op-amp is available to implement closed-loop control of the lamp current during normal lamp burning. to avoid cross conduction of the power mosfets the internal logic ensures a minimum deadtime. moreover the l6574 is prov ided with two lamp status control functions to protect the application against lamp failure as well as lamp disconnection. finally it is
high-frequency ballast AN2708 16/42 possible to modulate the output power in order to allow dimming by varying the switching frequency. the ballast operating frequencies determine the l6574 biasing circuitry as explained in an993 "electronic ballast with pfc using l6574 and l6561" and as summarized below. 2.2.1 lamp dimming in this system the lamps are dimmed down to 5% by interfacing the st7fdali microcontroller with the analog driver l6574. a pwm output of the st7fdali microcontroller is used to generate a 0-5 v pwm at 4 khz. its integrated value gives the op amp voltage reference. the dimming level is set by varying the pwm duty cycle from 70% (100% dimming) to 14% (5% dimming). this modification allows changing the l6574 op-amp positive reference voltage from 120 mv to 20 mv which increases the switching frequency and reduces the current in the load. on the slave unit the duty cycle values have been calculated accordin g the dali protocol brightness values, listed in figure 7 . table 8. l6574 biasing circuitry desi gn equations for operating conditions pin 1 (cpre) pin 2 (rpre) pin 3 (cf) pin 4 (rign) pin 5 (opout) a capacitor is connected between this pin and opin- for the current feedback loop compensation. it set also the turn on delay in a dimming application. t ph 1.5 c pre ? = t sh k pre 10 ----------------- c pre ? = fph frun ? 1.41 r pre cf ------------------------ = frun 1.41 rigncf -------------------- = frun 1.41 rigncf -------------------- =
AN2708 high-frequency ballast 17/42 figure 7. dali protocol brightness values to avoid the presence of stationary waves along the tubes at minimum dimming level, a resistor of 100 k ? / 2 w has been placed in parallel to the battery capacitor of each lamp. the resistance value ensures an additional current of 2 ma on the cathodes without affecting the ballast efficiency. finally, during the startup sequence the frequency always goes from fmax to fmin, independently of the set dimming level. only after lamp turn-on does the frequency move towards higher values. 2.2.2 supply section to supply the dali slave microcontroller an ac-dc buck converter based on the viper12a-e and l78l05 has been implemented on the ballast board. it converts the rectified and filtered mains to a 5 v regulated output voltage dedicated to the microcontroller. the converter works in discontinuous current mode adjusting the duty cycle
high-frequency ballast AN2708 18/42 of the viper12a-e power switch in order to deliver the energy from the input to the output by means of an inductor. pwm driver, power switch, thermal and overcurrent protection are integrated in the same silicon chip ensuring minimum si ze and good performances at very low cost. thanks to this implementation strategy the microcontroller is always supplied, allowing the lamps to turn on, even when l6562 and l6574 are in a latched shutdown state. the startup procedure is very important in an application that contains two different sections. the ballast section starts before the pfc, avoiding any extra voltage at the pfc section output, and consequently the l6562 ovp activation. this behavior is guaranteed under all conditions because the vs turn-on threshold of l6574 is lower than that of the l6562. the turn-on threshold is reached by a resistor chosen in order to ensure the startup current of both the l6562 and the l6574. when the ballast section is running, the charge pump (c11, r14, d3 and dz1) supplies both the devices and the filter r17-c10 allows to reduce the noise at vcc. 2.2.3 lamp turn-on and lamp turn-off to get low-power consumption (less than 0.6 w) during the lamps? turnoff state, both the half-bridge and the pfc have to be disabled, even in the presence of the mains at the ballast input. to manage this standby condition the l6574 control section and the l6562 zcd pin are interfaced with the dali slave microcontroller. short pulses (> 200 nsec) at the en1 and en2 inputs are recognized by the l6574. in particular, en1 high (> 0.6 v) stops all the half-bridge functions and puts the l6574 in a latched shutdown state. at the same time, by forcing externally the zcd pin to a voltage below 150 mv, the l6562 is stopped. to cancel this status, in order to turn on the lamps, a pulse (>0.6 v) is sent by the microcontroller to the l6574 second control pin en2 and the zcd pin external pull down is removed. the half-bridge driver restarts the preheating and ignition procedure, and the l6562 performs agai n its operation. the controls timing diagram is shown in figure 8 .
AN2708 high-frequency ballast 19/42 figure 8. ballast controls timing chart on the slave unit the turning on/off process is implemented by setting the pins pb3 (en1) and pb4 (en2) as output pull-up, while pb2 (zcd) as output open drain. the three corresponding bits in the port data register are clear by software. to "switch on" the ballast, a pulse must be sent to pb4 (en2 signal) and the third bit must be set in the port b (zcd) data register. to "switch off" the ballast, a pulse must be sent to pb3 (en1 signal) and the third bit must be cleared in the port b (zcd signal) data register. figure 9 , 10 , and 11 show the idle state and the turn-on/off commands. vsupply en1 lvg hvg en2 zcd gd time latched disable forced restart
high-frequency ballast AN2708 20/42 figure 9. idle state figure 10. turn-on procedure figure 11. turn-off procedure ch3 (blue): en1 low level ch4 (green): en2 low level ch3 (blue): en1 low level ch4 (green): en2 pulse ch3 (blue): en1 pulse ch4 (green): en2 low level
AN2708 high-frequency ballast 21/42 2.2.4 verification of lamp status this function detects a lamp disconnection or a lamp failure on the slave board. the microcontroller performs a double check: one on the pb1 pin for the lamp hardware status and one on the flag "lamp_arc_power_on" for the lamp software status. if the pb1 logical level is low and the flag is true, lamp disconnection happened. the condition is recorded on st7fdali, so when the microcontroller receives a "query frame" from the master, it changes the pb3 (en1) and pb4 (en2) configuration from input to output, and sends a byte answer as 'status information' described below: bit 0 status of ballast; '1'= nok bit 1 lamp failure; '1'= nok bit 2 lamp arc power on; '0' = off bit 3 query: limit error; '0' = last requested arc power level is between min..max level or off bit 4 fade ready; '0' = fade is ready; '1' = fade is running bit 5 query: 'reset state'? '0' = 'no' bit 6 query: missing short address? '0' = 'no' bit 7 query: 'power failure'? '0' = 'no' ; 'reset' or an arc po wer control command has been received after last power-on when the master receives this frame, it displays the lamp status by means of two leds (green stands for ok, red for status not ok). once the failure condition has been detected and solved, an "on" command has to be sent to the slave, allowing the master's microcontroller to toggle again the led status from red to green. from the analog side, to detect a disconnection or a failure event for each lamp, two signal schottky diodes have been used to bias the en1 or en2 pin of l6574. the failure condition is detected both at startup and when running. the forward and backward frame timing is shown in figure 12 and 13 : figure 12. forward frame timing
high-frequency ballast AN2708 22/42 figure 13. backward frame timing the forward as well as the backward frame duration is the same for all kinds of commands. 2.2.5 ballast performances in this section the main ballast waveforms are shown. figure 14. ballast startup at 230 vac-full power figure 15. lamps turn-on at 230 vac-full power ch2 (blue): lamp current ch3 (magenta): v cpre ch4 (green): supply voltage ch1 (yellow): lamp1 voltage ch2 (blue): lamp1 current ch3 (magenta): lamp2 voltage ch4 (green): lamp2 current
AN2708 high-frequency ballast 23/42 figure 16. lamps running at 230 vac - full power the efficiency of the system is a little bit lower than a standard hf ballast due to the supply section of the slave and the resistors in series to the lamp?s cathode used to ensure a minimum current at low dimming level. table 9. ballast performances vin (vac) pin (w) pf thd (%) po (w) (%) 90 76.5 0.999 3.9 66 86.2 110 75.5 0.999 3.6 66 87.4 140 74.2 0.998 5.5 66 89 176 73.7 0.997 7.2 66 90 230 73 0.997 7.3 66 90 265 72.8 0.996 8.3 66 91 ch1 (yellow): lamp1 voltage ch2 (blue): lamp1 current ch3 (magenta): lamp2 voltage ch4 (green): lamp2 current
dali master unit AN2708 24/42 3 dali master unit the st2c334j4 microcontroller is used as master, implementing the dali peripheral via software. the communication master-slave uses a 20 v bus. to adapt the ttl level of the microcontroller to the communication bus level, two opto-couplers and a npn transistor bc- 817 have been used. the rs232 interface with st232c is available on the board to implement the sci communication as an option. this option expects the use of a pc to address the ballast either with broadcast or group or single mode thanks to a gui called (dali power control). the dali master unit has been thought of as a standalone solution. in fact it is provided with a keyboard to manage the dali commands, to address the slaves and to display the lamps? status. the keyboard is made up of 16 push buttons controlled by means of a matrix representation. in particular the first four pins of portd are associated to the rows and the first four pins of portb to the columns. the check of the keyboar d is implemented as a loop mode by clearing the pddr register port and setting the pbdr register port sequentially. when a button is pressed, the pin of the port b corresponding to the interested column goes down and this condition is taken over by an interrupt condition. inside the interrupt routine, a read procedure of the port registers pddr and pbdr is expected and by this information the pressed button is acknowledged. the ?press button? procedure is described by figure 17 and 18 . figure 17. polling keyboard ch1 (yellow): row polling ch2 (purple): column level
AN2708 dali master unit 25/42 figure 18. pressed button event ch1 (yellow): row polling ch2 (purple): column level
dali master unit AN2708 26/42 3.1 master unit schematic and bill of material the schematic of the master unit is shown in figure 19 . figure 19. master unit schematic red red r74 220r 5% 1w 5vdd r84 4r7 1% r83 330r 1% r85 3k 1% ain4 1 1 2 2 3 3 4 4 u15 sfh6156-2 r79 11k 1% ain5 + c55 22uf ld3 ls m67k-h2l1-1 ld4 lg m67k-g1j2-24 1 4 2 3 - + d20 mb2s ain4 pf2 ain5 pb4 pa3 5vdd ain4 query status slave address query status 5vdd sw1 reset vd 1 2 3 4 5 6 7 8 9 10 11 12 13 j9 ain5 pf2 pb4 col2 d26 lg m67k-g1j2-24 col4 col3 col1 d25 ls m67k-h2l1-1 d24 lg m67k-g1j2-24 row2 row1 row4 row3 d23 ls m67k-h2l1-1 pa3 row1 d28 lg m67k-g1j2-24 d27 lg m67k-g1j2-24 d22 bz84c 2v7 r86 1k r87 1k col4 r77 0 row2 r88 1k 5vdd r75 10k 1% col3 row3 r89 1k row4 r78 1k2 1% r90 1k ain0/pd0 2 ain1/pd1 3 ain2/pd2 4 ain3/pd3 5 ain4/pd4 6 ain5/pd5 7 mc o/ pf 0 10 beep/pf1 11 pf2 12 ocmp1_a/pf4 13 icap1_a/(hs)/pf6 14 extclk_a/(hs)/pf7 15 ocmp2_b/pc0 16 ocmp1_b/pc1 17 icap2_b/(hs)/pc2 18 icap1_b/(hs)/pc3 19 ispdata/miso/pc4 20 mosi/pc5 21 sck/ispclk/pc6 22 ss'/pc7 23 osc1 35 osc2 34 pa3 24 pa4(hs) 27 pa5(hs) 28 pa6(hs) 29 pa7(hs) 30 vdda 8 vdd_1 25 vdd_2 36 vss_1 26 vss_2 33 vssa 9 pb0 39 pb1 40 pb2 41 pb3 42 pb4 1 pe0/td0 37 pe1/rd1 38 reset 32 ispsel 31 u12 st72c334j4b6 5 9 4 8 3 7 2 6 1 p1 rs232 c1+ 1 v+ 2 c1- 3 c2- 5 v- 6 t2ou t 7 r2in 8 c2+ 4 r2out 9 t2i n 10 t1i n 11 r1in 13 t1ou t 14 r1out 12 vdd 16 gnd 15 u13 st232c col2 y1 16mhz r91 1k col1 1 1 2 2 3 3 4 4 u14 sfh6156-2 c53 100nf 50v 5vdd c47 100nf 50v 5vdd c51 100nf 50v c52 100nf 50v c48 100nf 50v tr an sm. transm. r82 4.7k c54 100nf c50 100nf 50v 5vdd c49 220nf 50v r80 1k r81 1k d21 bas16 + 1 + 3 + 5 + 7 + 9 + 2 + 4 + 6 + 8 + 10 j8 icp connector 5vdd 5vdd pb4 5vdd r76 10k 1% 3 2 1 q5 bc817-25 pa3 1 2 j6 dali bus 1 2 3 j7 supply voltage r73 0 5% d19 bzx85c22 50v 25v green green green green row2 red row4 row3 green row1 sw19 sw18 sw20 sw21 sw22 sw23 sw24 sw25 sw26 sw27 sw28 sw29 sw30 sw31 sw32 sw33 porta pb0 colomn4 porta pd3 row4 porta pb1 colomn3 porta pb3 colomn1 porta pb2 colomn2 porta pd2 row3 porta pd0 row1 porta pd1 row2 r102 10k columns rows 1 2 3 j18 pull-up jumper 5vdd col2 col1 col4 col3
AN2708 dali master unit 27/42 table 10. master unit bill of material reference value description c47,c48,c50,c51,c52, c53,c54 100 nf 50 v ceramic capacitor smd 0805 c49 220 nf 50 v ceramic capacitor smd 0805 c55 22 f 25 v tantalum capacitor smd d19 bzx85c22 22 v 0.5 w zener diode d20 mb2s smd bridge rectifier d21 bas16 smd diode d22 bz84c 2v7 2.7 v 0.5 w zener smd diode d23,d25 ls m67k-h2l1-1 red smd led 2 ma, 0805 d24,d26,d27,d28 lg m67k-g1j2-24 green smd led 2 ma, 0805 j6 dali bus 2-way single row, header shrouded j7 supply voltage 3-way single row header shrouded j8 icp connector 10-way 2-row vertical through-hole boxed header, 2.54 mm pitch/grid j9 13-way strip line connector (not mounted) j12 pull-up jumper 3-way strip line connector ld3 ls m67k-h2l1-1 red smd led 2 ma, 0805 ld4 lg m67k-g1j2-24 green smd led 2 ma, 0805 p1 serial connector 9-way 90 pcb mount d plug q5 bc817-25 smd npn transistor r73 0 resistor smd 1206 r77 0 resistor smd 0805 r74 220 ? 1 w 5% resistor r75,r76 10 k ? 1% resistor smd 0805 r78 1.2 k ? 1% resistor smd 0805 r79 11 k ? 1% resistor smd 0805 r80,r81 1 k ? resistor smd 0805 r82 4.7 k ? resistor smd 0805 r83 330 ? 1% resistor smd 0805 r84 4.7 ? 1% resistor smd 0805 r85 3 k ? 1% resistor smd 0805 r86,r87,r88,r89,r90, r91 1 k ? resistor smd 0805 r101 10 k ? resistor smd 0805 sw1 reset tht button
dali master unit AN2708 28/42 note: resistors are 0.25 w unless specified sw2, sw3, sw4, sw5, sw6, sw7, sw8, sw9, sw10, sw11, sw12, sw13, sw14, sw15, sw16, sw17 keyboard tht button u12 st72c334j4b6 psdip42 stmicroelectronics 8-bit mcu with single voltage flash memory, adc, 16-bit timers, spi, sci interface u13 st232c sop stmicroelectronics 5 v powered multi-channel rs-232 drivers and receivers u14,u15 sfh6156-2 smd opto-coupler y1 16 mhz oscillator table 10. master unit bill of material (continued) reference value description
AN2708 basics of dali 29/42 4 basics of dali dali stands for "digital addressable lighting interface". it is a standard interface for lighting control solutions, defined by the main lighting manufacturers and standardized as iec 929. the dali protocol is implemented on a master-slave architecture. it uses the bi-phase manchester asynchronous serial data format. all the bits of the frame are bi-phase encoded except the two stop bits. following are some of the standard features: transmission rate at 1.2 khz. bi-phase bit period is 833.33 s 10%. a forward frame consists of 19 bi-phase encoded bits: ? 1 start bit (0->1: logical '1') ? 1 address byte (8-bit address) ? 1 data byte (8-bit data) ? 2 high level stop bits (no change of phase) a backward frame consists of 11 bi-phase encoded bits: ? 1 start bit (0->1: logical '1') ? 1 data byte (8-bit data) ? 2 high level stop bits (no change of phase) each frame has 2 stop bits which do not contain any change of phase. the setting time between two subsequent forward frames is 9.17 ms (minimum), while the delay between forward and backward frame goes from 2.92 ms to 9.17 ms. if a backward frame has not been started after 9.17 ms, this is interpreted as "no answer". in the event of code violatio n, the frame is ignored and the system is ready again for data reception. the main advantages of the dali system can be summarized as follows: simple wiring: all of the units in the system are interconnected using a simple five-core cable. figure 20. cable wiring
basics of dali AN2708 30/42 no mains switching required: lamps can be dimmed or switched on and off using control system commands without any need for mains switching. easy system re-configuration: the configuration of the system can be changed quickly without any modification to the hardware. easy system modification: if the lighting system needs to be enlarged, new components can be added anywhere on the dali cable. it is possible to define light scenes. a scene means a particular light level intensity. 16 scenes can be defined at maximum. figure 21. master flowchart start polling keyboard push button button number 11 change slave address send command query frame wait backward frame frame received toggle led no answer n y n y y n n y
AN2708 basics of dali 31/42 figure 22. slave flowchart start main process command pin pb1=low level failure=1 on/ off pulse on en1(off) or en2 (on) change pin confi g uration pwm routine query command change configuration of pb3 , pb4 p in send lamp failure failure=1 other indirect arc power control comman d s send lamp ok dali peripheral new frame received y n y n y n y n y n
dali master ac-dc adapter AN2708 32/42 5 dali master ac-dc adapter this is an offline wide-range double-output smps based on the viper12a-e. the first output, 20 v at 100 ma, is dedicated to the bus communication allowing to address up to 64 slaves, while the second one delivers 5 v at 10 ma to the master dali microcontroller thanks to a linear post-regulator. the viper12a-e combines on the same silicon chip a dedica ted current mode pwm controller, a high voltage power mosfet and the protection features (thermal, overcurrent, and overvoltage) which increases the converter reliability and saves size, parts count and cost. the converter topology is an isolated flyback designed to work in discontinuous current mode according to the following specifications: 5.1 adapter description the schematic of the board is shown in figure 23 . the ac input is rectified by the diodes bridge and then filtered by the bulk capacitor c1, and c2 to generate the high voltage dc. the input emi filter is a simple clc pi filter for both differential and common mode noise suppression. an ntc limits the inrush current and ensures a reliable operation of the bridge at startup. the switching frequency is fixed at 60 khz by the ic internal oscillato r allowing optimization of the transformer size and cost. an rcd sn ubber circuit (r92, c59, d30) reduces the leakage inductance voltage spike and the voltage ringing on the drain pin of viper12a-e. as soon as the voltage is applied on the input of the converter the high voltage startup current source connected to the drain pin is activated and starts to charge the vdd capacitor c8 by a constant current of 1ma. when the vo ltage across this capacitor reaches the vddon threshold (about 14 v) the viper12as-e starts to switch. during normal operation the smart table 11. smps operating conditions parameter value input voltage range 90 ? 265 vac input frequency range 50/60 hz output voltage 1 v1=20 v output voltage 2 v2=5 v output current 1 i1=100 ma output current 2 i2=10 ma output power (peak) 2.2 w line regulation +/- 1% load regulation +/- 1% emi en55015
AN2708 dali master ac-dc adapter 33/42 power ic is powered by the auxiliary winding of the transformer via the diode d31. no spike killer for the auxiliary vo ltage fluctuations is needed thanks to the wide rang e of the vdd pin (9-38 v). the primary current is measured using the integrated current sensing for current mode operation. the output rectifier d29 has been chosen in accordance with the maximum reverse voltage and power dissipation. in particular a 1 a - 150 v power schottky, type stps1150, has been selected. the output voltage regulation is performed by secondary feedback on the 20 v output while the 5 v output, is linearly post-regulated from the 20 v output. this operation is performed by a low drop voltage regulator, l78l05cz, in the to92 package. the feedback network consists of a programmable voltage reference, tl431, driving an optocoupler which ensures the required insulation between the primary and secondary sections. the optotransistor drives directly the viper12a-e feedback pin which controls the operation of the ic. a small lc filter has been added on the 20 v output in order to reduce the high frequency ripple with reasonable output capacitor value. the flyback transformer is a layer type based on the ef13 core and fi 324 ferrite, manufactured by vogt, and ensures safety insulation in accordance with the en60950. figure 26 shows the main features of the transformer. the power supply has been implemented on a double-sided 35 m pcb in fr-4, sizing 81 x 37 mm. figure 23. adapter schematic 1 2 j17 input 250v con r98 150k r96 33k c65 10nf 1 2 4 3 u17 pc817 2 1 3 u19 tl431 c64 100nf r99 4.7k 50v 50v 50v vin 3 vout 1 gnd 2 u16 l78l05cz 1 2 9 6 4 5 t3 sl 060 918 11 01 + c62 2.2uf c58 470pf 1 2 3 j10 supply voltage r92 56k 400v 400v d30 stth1l06 l8 100uh 600ma 35v ntc2 10r @ 25 fuse2 0.5a + c56 2.2uf + c57 2.2uf l9 1mh 130ma r94 10r 35v d29 stps1150 + c59 150uf r97 10k 1kv + c60 22uf + c63 10uf d 8 vdd 4 fb 3 s 1 s 2 d 7 d 6 d 5 u18 viper12a 20v@100ma c61 2.2nf y 1 5v@10ma d31 1n4148 t1: smt - ef12.6/3.7core, fi324 f errite - 0.16mm gap f or 2mh primary inductance - primary : 135 turns (0.14mm-awg35) - secondary : 28 turns (0.36mm-awg27) - auxiliary : 21 turns (0.05mm-awg44) 1 4 3 2 -+ bridge2 df06 r93 560r r95 1k
dali master ac-dc adapter AN2708 34/42 figure 26. flyback transformer operating switching frequency: 60 khz core geometry: ef 12.6/3.7 core material: fi 324 or equivalent primary inductance value: 2 mh leakage inductance: 75 h air gap length: 0.16 mm safety: en60950 figure 24. adapter pcb layout - top side - silkscreen (to scale) figure 25. adapter pcb layout - bottom side - copper tracks (to scale)
AN2708 dali master ac-dc adapter 35/42 5.2 adapter bill of material table 12. adapter bill of material reference value description bridge2 df06m 1 a 600 v bridge rectifier c56,c57 2.2 f 400 v electrolytic cap c58 470 pf 1 kv ceramic cap c59 150 f 35 v low esr electrolytic cap c60 22 f 35 v low esr electrolytic cap c61 2.2 nf y1 y1 ceramic cap c62 2.2 f 25 v electrolytic cap c63 10 f 50 v electrolytic cap c64 100 nf 50 v ceramic cap c65 10 nf 50 v ceramic cap d29 stps1150 stmicroelectronics po wer schottky rectifier 1 a 150 v d30 stth1l06 stmicroelectronics ultrafast high-voltage rectfifier 1 a 600 v d31 1n4148 small signal rectifier 200 ma 100 v fuse2 0.5 a radial fuse j10 supply voltage 3-way single row shrouded header j11 input 250 v connector 2-way pcb screw terminal, 5.08 mm l8 100 h 600 ma axial inductor l9 1 mh 130 ma axial inductor ntc2 10 ? @ 25 inrush current suppressor r92 56 k ? resistor, metal film 0.25 w r93 560 ? resistor, metal film 0.25w r94 10 ? resistor, metal film 0.25 w r95 1 k ? resistor, metal film 0.25 w r96 33 k ? resistor, metal film 0.25 w r97 10 k ? resistor, metal film 0.25 w r98 150 k ? resistor, metal film 0.25 w r99 4.7 k ? resistor, metal film 0.25 w t3 sl 060 918 11 01 vogt smt u16 l78l05cz to92 stmicroelectronics positive voltage regulator u17 pc817 sharp optocoupler 5 kv u18 viper12a-e dip8 stmicroelectronics offline smps primary ic 730 v 0.4 a 27 ? u19 tl431 to92 stmicroelectronics programmable voltage reference
dali master ac-dc adapter AN2708 36/42 5.3 adapter performances several tests have been performed on the board to evaluate the converter behavior in terms of efficiency, stability, safe operating area of the devices, line & load regulation and emi performances. 5.3.1 steady state tests these tests have been performed at the input voltage of 110 vac and 230 vac at full and minimum load condition. as shown by the waveforms the power supply operates in discontinuous current mode. figure 27. viper12a-e steady state behavior at f u l l l o a d a t 1 1 0 v a c - 6 0 h z figure 28. viper12a-e steady state behavior at full load at 230 vac - 50 hz ch1 (blue): drain voltage ch4 (purple): drain current ch1 (blue): drain voltage ch4 (purple): drain current figure 29. viper12a-e steady state behavior at minimum load at 110 vac - 60 hz figure 30. viper12a-e steady state behavior at minimum load at 230 vac - 50 hz ch1 (blue): drain voltage ch4 (purple): drain current ch1 (blue): drain voltage ch4 (purple): drain current
AN2708 dali master ac-dc adapter 37/42 at minimum load the viper12a-e ensures the burst mode operation, saving the input power consumption. 5.3.2 startup behavior figure 31 , 32 , 33 , and 34 show the typical waveforms during the startup of the power supply. in particular, the full load cond ition is considered since it re presents the heaviest case in terms of voltage and current stress, as well as the minimum load condi tion for loop stability and voltage stress. figure 31. startup waveforms at full load at 110 vac - 60 hz figure 32. startup waveforms at full load at 230 vac - 50 hz ch1 (blue): drain voltage ch2 (red): 5 vout ch3 (green): 20 vout ch4 (purple): drain current ch1 (blue): drain voltage ch2 (red): 5 vout ch3 (green): 20 vout ch4 (purple): drain current
dali master ac-dc adapter AN2708 38/42 there is no overshoot on the output voltages and the measured wakeup time is 180 ms. 5.3.3 dynamic load tests these tests show the transient load response at 110 vac and 230 vac mains when the 20 v output current is increased from 10% to 90% of the maximum value. in the worst case the result is 224 mv or 1.12% of dynamic load regulation which indicates a very good dynamic behavior. figure 33. startup waveforms at minimum load at 110 vac - 60 hz figure 34. startup waveforms at minimum load at 230 vac - 50 hz ch1 (blue): drain voltage ch2 (red): 5 vout ch3 (green): 20 vout ch4 (purple): drain current ch1 (blue): drain voltage ch2 (red): 5 vout ch3 (green): 20 vout ch4 (purple): drain current figure 35. dynamic load waveforms at 110 vac - 60 hz figure 36. dynamic load waveforms at 230 vac - 50 hz ch3 (green): 20 vout voltage ripple ch4 (purple): 20 vout current ch3 (green): 20 vout voltage ripple ch4 (purple): 20 vout current
AN2708 dali master ac-dc adapter 39/42 5.3.4 line regulation for this test the output power is kept at the peak value (2.2 w) while the line voltage is slowly increased from 85 vac to 265 vac. the board has a line regulation of +0.9%. figure 37. line regulation 5.3.5 load regulation as the 5 v output is obtained by a linear regulator, the load regulation measurements have been performed only on 20 v output by changing its load from 10 ma to full load 100 ma. the input voltage is kept at the nominal value of 230 vac. the board has a load regulation of +0.9%. figure 38. load regulation 1 3 5 7 9 11 13 15 17 19 21 23 70 80 90 100 110 120 140 160 170 180 190 200 210 220 230 240 250 260 270 290 310 input voltage (vac) output voltage (vdc) 20vout 5vout 16 17 18 19 20 21 22 23 24 0 102030405060708090100110 output current (ma) 20v output (vdc) 20v output
dali master ac-dc adapter AN2708 40/42 5.3.6 efficiency variation for this test the efficiency is measured when the line input is varied from 85 vac to 264 vac at full load. the average efficiency is 66.5%. a moderate value is typical of low power applications. figure 39. efficiency variations vs. input voltage at full load 5.3.7 conducted emissions test conducted emissions have been measured in neutral and line wires, using peak detector and considering the limits for lighting applications i.e. en55015. the measurements have been performed at 110 vac and 230 vac line with fully loaded outputs. the results are shown in figure 40 , 41 , 42 , and 43 . since the emission level is below both the quasi-peak and average limits with acceptable margin, the power supply passes the pre-compliance test. 50 52.5 55 57.5 60 62.5 65 67.5 70 72.5 75 77.5 80 70 80 90 100 110 120 140 160 170 180 190 200 210 220 230 240 250 260 270 290 310 input voltage(vac) effiiciency (%) efficiency figure 40. conducted emissions at 110 vac 60 hz - full load - line 1 peak detector figure 41. conducted emissions at 110 vac 60 hz - full load - line 2 peak detector 01:55:30 apr 10, 2007 ref 75 db v# atten 10 db peak log 10 db/ w1 s2 s3 fc aa start 150 khz res bw 9 khz vbw 30 khz stop 30 mhz sweep 881.3 ms (2115 pts) 01:55:07 apr 10, 2007 ref 75 db v# atten 10 db peak log 10 db/ w1 s2 s3 fc aa start 150 khz res bw 9 khz vbw 30 khz stop 30 mhz sweep 881.3 ms (2115 pts)
AN2708 references 41/42 6 references 1. "l6561, enhanced transition mode power factor corrector" (an966) 2. "switching from the l6561 to the l6562" (an1757) 3. "control loop modelling of l6561-based tm pfc" (an1089) 4. "electronic ballast with pfc using l6574 and l6561" (an993) 5. "choosing a dali implementation strategy with st7dali" (an1756) 6. "hardware implementation for st7dali-eval" (an1900) 7 revision history figure 42. conducted emissions at 230 vac 50 hz - full load - line 1 peak detector figure 43. conducted emissions at 230 vac 50 hz - full load - line 2 peak detector 01:53:40 apr 10, 2007 ref 75 db v# atten 10 db peak log 10 db/ w1 s2 s3 fc aa start 150 khz res bw 9 khz vbw 30 khz stop 30 mhz sweep 881.3 ms (2115 pts) 01:54:24 apr 10, 2007 ref 75 db v# atten 10 db peak log 10 db/ w1 s2 s3 fc aa start 150 khz res bw 9 khz vbw 30 khz stop 30 mhz sweep 881.3 ms (2115 pts) table 13. document revision history date revision changes 07-mar-2008 1 initial release
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